Lattice LCMXO2280 MachXO Mini评估开发方案 - FPGA/CPLD - 电子工程网
Lattice公司的MachXO系于是非易失可无限次配置的可编程逻辑器件(PLD),具有256到2280个LUT,I/O数多达271个,多达27.6Kb sysMEM嵌入区块RAM(EBR)和多达7.7Kb的分布式RAM,支持IEEE 标准1149.1 边界扫描,工作电压而不服.3V,2.5V,1.8V或1.2V.主要用在低密度的工业控制,医疗电子,汽车电子,通信和消费电子等领域.本文介绍了MachXO 系列主要特性以及MachXO Mini 开发套件主要特性与MachXO Mini评估板方框图,电路图和材料清单.
The MachXO family of non-volatile infinitely reconfigurable Programmable Logic Devices (PLDs) is designed for applications traditionally implemented using CPLDs or low-density FPGAs. Widely adopted in a broad range of applications that require general purpose I/O expansion, interface bridging and power-up management functions, MachXO PLDs offer the benefits of increased system integration by providing embedded memory, built-in PLLs, high performance LVDS I/O, remote field upgrade (TransFRTM technology) and a low power sleep mode, all in a single-device.
Designed for a broad range of low density applications including system control designs, the MachXO PLD family is used in a variety of end markets including consumer, automotive, communications, computing, industrial and medical.
The MachXO is optimized to meet the requirements of applications traditionally addressed by CPLDs and low capacity FPGAs: glue logic, bus bridging, bus interfacing, power-up control, and control logic. These devices bring together the best features of CPLD and FPGA devices on a single chip.
The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flex-ible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, high-security, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and careful design will provide the high pin-to-pin performance also associated with CPLDs. The ispLEVER reg; design tools from Lattice allow complex designs to be efficiently implemented using the MachXO family of devices. Popular logic synthesis tools provide synthesis library support for MachXO. The ispLEVER tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the MachXO device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification.
Non-volatile, Infinitely Reconfigurable
Instant-on – powers up in microseconds
Single chip, no external configuration memory required
Excellent design security, no bit stream to intercept
Reconfigure SRAM based logic in milliseconds
SRAM and non-volatile memory programmable through JTAG port
Supports background programming of non-volatile memory
Allows up to 100x static current reduction
TransFR Reconfiguration (TFR)
In-field logic update while system operates
High I/O to Logic Density
256 to 2280 LUT4s
73 to 271 I/Os with extensive package options
Density migration supported
Lead free/RoHS compliant packaging
Embedded and Distributed Memory
Up to 27.6 Kbits sysMEM Embedded Block RAM
Up to 7.7 Kbits distributed RAM
Dedicated FIFO control logic
Flexible I/O Buffer
Programmable sysIO buffer supports wide range of interfaces: LVCMOS 3.3/2.5/1.8/1.5/1.2 LVTTL PCI LVDS, Bus-LVDS, LVPECL, RSDS
Up to two analog PLLs per device
Clock multiply, divide, and phase shifting
System Level Support
IEEE Standard 1149.1 Boundary Scan
Devices operate with 3.3V, 2.5V, 1.8V or 1.2V power supply
IEEE 1532 compliant in-system programming